1. Field of the Invention
The present invention relates to the transfer of data blocks from a source device to a destination device, and particularly to combining transfer indications to a host processor.
2. Description of Related Art
Typically, when a data block is transferred from a source device to a destination device on a data bus in a host system at least two indication signals are generated. The source device generates the indication signals to a host processor describing the status of the transfer. A first indication signal is generated which may produce an interrupt signal to a host processor when the source device is ready to transfer a block of data to the destination device, such as system memory. The host processor then will respond to the interrupt signal by saving its system parameters and entering its interrupt service routine. However, saving the host processor's system parameters and entering an interrupt service routine degrades system performance. Not only is the host processor unable to carry out other functions during this state of operation, the saving of system parameters takes a relatively long period of time. For example, the saving of system parameters in an OS/2 operating system may take as long as 30 microseconds.
During the interrupt service routine of the host processor, a determination will be made as to which device on the data bus generated the interrupt and what service is required. In the case that the interrupt was generated by a source device which needs to transfer a block of data to a destination device, the host processor will initiate the transfer to the destination device. The host processor will then exit the interrupt service routine and continue its previous state of operation.
The second indication signal generated by the source device occurs when the transfer of a block of data is complete. This second indication signal also may generate a second interrupt to the host processor. Once again, system performance is slowed by the host processor entering its interrupt service routine for the second time and determining the cause of the interrupt and servicing the interrupt.
Generally two indication signals generate two interrupt signals to a host processor when a single block of data is transferred with each interrupt signal reducing system performance. The first interrupt is generated when a block of data is ready for transfer, and the second interrupt is generated when the transfer of the block of data is complete.
Moreover, interrupts generated by a transfer of one block of data may occur relatively close in time to the interrupts generated by the availability of a second block of data. The second interrupt generated by the first data block transfer complete indication may occur right before a first interrupt of a second block of data generated by a ready for transfer indication. Both interrupts occurring in a relatively short period of time cause the host processor to enter back-to-back interrupt service routines.
Therefore, it is desirable to provide a device which combines indication signals to the host processor for both the ready for transfer of a second block of data and the completion of transfer of the first block of data in a single interrupt. The combining of indication signals would reduce the number of interrupts generated to the host processor during the transfer of blocks of data allowing for optimized host system performance and in particular host processor performance.